1. Field
This disclosure pertains to the field of system-on-a-chip integrated circuit devices, and more particularly, to a system-on-a-chip storing chip data and/or security data for the chip, and a method of processing chip data and/or security data for a system-on-a-chip.
2. Description
System-on-a-chip or system on chip (SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). An SOC may contain digital, analog, mixed-signal, and often radio-frequency functions—all on one chip. A typical application is in the area of embedded systems. In general an SOP includes a number of functional blocks. These functional blocks are typically realized as intellectual property (IP) blocks or cores.
An IP block, or IP core, is a reusable unit of logic, cell, or chip layout design that is also the intellectual property of one party. IP cores may be licensed to another party or can also be owned and used by a single party alone. The term is derived from the licensing of the patent and copyright intellectual property rights that subsist in the design. IP cores can be used as building blocks within application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) designs. Ideally, an IP core should be portable—that is, able to easily be inserted into any vendor technology or design methodology. An IP core may be a hard core, a firm core, or a soft core. IP cores in the electronic design industry have had a profound impact on the design of SOCs.
FIG. 1 illustrates an example of a system-on-a-chip (SOC) 10. SOC 10 includes memory system 100 and data processor 200. Memory system 100 includes memory 110, memory controller 120, and error correction code (ECC) decoder 130. Data processor 200 includes a plurality of functional blocks 210-1˜210-N and an interface 220 for communicating data between data processor 200 and memory system 100.
Memory 110 stores user data generated or processed by data processor 200 and its functional blocks 210-1˜210-N during operations of SOC 10, under control of memory controller 120. ECC decoder 130 performs an error correction code decoding operation for user data or application data when it is communicated from memory system 100 to data processor 200.
Each of the functional blocks 210-1˜210-N includes logic and/or data to perform one or more operations of SOC 10.
In many cases, SOC 10 has certain chip information and/or security information for the SOC stored therein. This information may include a variety of data, including for example, a chip identification number, a chip version number, a chip security code, etc. Chip information and security information for the SOC should be distinguished from user data or application data generated and/or processed by data processor 200 and its functional blocks 210-1˜210-N during operations of SOC 10.
In general, this data is stored in a read only memory (ROM) of SOC 10, which is generally a one-time programmable ROM, such as an E-Fuse ROM. The chip information and/or security information for SOC 10 is fixed in the ROM during the chip manufacturing process.
However, a problem occurs sometimes such that there is a malfunction or failure in the process of storing the chip information and/or security information for SOC 10 in the ROM, such that the correct data is not stored, or is stored in poor quality. This reduces the manufacturing yield for SOC 10.
Accordingly, it would be desirable to provide a system-on-a-chip (SOC) that is able to recover from a defect or malfunction in storing chip information and/or security information for the SOC during the manufacturing process. It would be further desirable to provide a method of operating a SOC when errors occur while storing in an SOC chip information and/or security information for the SOC during the manufacturing process.